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features description applications contents typical application diagram UCC28019 slus755 ? april 2007 8-pin continuous conduction mode (ccm) pfc controller 8-pin solution without sensing line voltage the UCC28019 8-pin active power factor correction reduces external components (pfc) controller uses the boost topology operating in continuous conduction mode (ccm). the controller wide-range universal ac input voltage is suitable for systems in the 100 w to >2 kw range fixed 65-khz operating frequency over a wide-range universal ac line input. startup maximum duty cycle of 97% current during under-voltage lockout is less than 200 a. the user can control low power standby mode output over/under-voltage protection by pulling the vsense pin below 0.77 v. input brown-out protection low-distortion wave-shaping of the input current cycle-by-cycle peak current limiting using average current mode control is achieved open loop detection without input line sensing, reducing the bill of low-power user controlled standby mode materials component count. simple external networks allow for flexible compensation of the current and voltage control loops. the switching frequency is internally fixed and trimmed to better ccm boost power factor correction power than 5% accuracy at 25c. fast 1.5-a gate peak converters in the 100 w to >2 kw range current drives the external switch. server and desktop power supplies numerous system-level protection features include telecom rectifiers peak current limit, soft over-current, open-loop industrial electronics detection, input brown-out, output home electronics over/under-voltage, a no-power discharge path on vcomp, and overload protection on icomp. soft-start limits boost current during start-up. a electrical characteristics 3 trimmed internal reference provides accurate protection thresholds and regulation set-point. an device information 10 internal clamp limits the gate drive voltage to 12.5 v. application information 12 design example 23 additional references 43 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com + C bridge rectifier line input v out emi filter UCC28019 r load gnd icomp isense gate vcc vsense vcomp vins 1 2 3 4 8 7 6 5 auxilary supply
absolute maximum ratings (1) dissipation ratings (1) recommended operating conditions electrostatic discharge (esd) protection UCC28019 slus755 ? april 2007 ordering information operating temperature part number package (1) range, t a UCC28019d soic 8-pin (d) ead (pb)-free/green ?40 c to 125 c plastic dip 8 pin (p) lead UCC28019p (pb)-free/green (1) soic (d) package is available taped and reeled by adding "r" suffix the the above part number, reeled quantities are 2500 devices per reel. over operating free-air temperature range (unless otherwise noted) value unit vcc ?0.3 to 22 gate ?0.3 to 16 input voltage range v vins, vsense, vcomp, icomp ?0.3 to 7 isense ?24 to 7 input current range vsense, isense ?1 to 1 ma operating ?55 to 150 junction temperature, t j storage ?65 to 150 c lead temperature, t sol soldering, 10s 300 (1) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those included under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability. package thermal impedance t a = 25 c power rating (w) t a = 85 c power rating (w) junction to ambient ( c/w) soic-8 (d) 160 0.65 0.25 pdip-8 (p) 110 1 0.36 (1) tested per jedec eia/jesd 51-1. thermal resistance is a strong function of board construction and layout. air flow reduces thermal resistance. this number is only a general guide. see ti document spra953 thermal metrics. over operating free-air temperature range (unless otherwise noted) parameter min max unit vcc input voltage from a low-impedance source vcc off(max) + 1 v 21 v t j operating junction temperature ?40 125 c over operating free-air temperature range (unless otherwise noted) parameter rating unit human body model (hbm) 2 kv charged device model (cdm) 500 v 2 submit documentation feedback www.ti.com
electrical characteristics UCC28019 slus755 ? april 2007 unless otherwise noted, vcc = 15 v dc , 0.1 m f from vcc to gnd, -40c t j = t a 125c. all voltages are with respect to gnd. currents are positive into and negative out of the specified terminal. parameter test conditions min typ max unit vcc bias supply i vcc(start) pre-start current vcc = vcc on ? 0.1 v 25 100 200 a i vcc(stby) standby current vsense = 0.5 v 1.0 2.1 2.9 ma i vcc(on_load) operating current vsense = 4.5 v, c gate = 4.7 nf 4 7 10 under voltage lockout (uvlo) vcc on turn on threshold 10.0 10.5 11.0 vcc off turn off threshold 9 9.5 10 v uvlo hysteresis 0.8 1.0 1.2 oscillator t a = 25c 61.7 65.0 68.3 f sw switching frequency, khz ? 40c t a 125c 59 65 71 pwm vcomp = 0 v, vsense = 5 v, d min minimum duty cycle 0% icomp = 6.4 v d max maximum duty cycle vsense = 4.95 v 94% 97% 99.3% t off(min) minimum off time vsense = 3 v, icomp = 1 v 100 250 600 ns system protection isense threshold, soft over current v soc -0.66 -0.73 -0.79 (soc) , isense threshold, peak current limit v pcl -1.00 -1.08 -1.15 v (pcl) , vsense threshold, open loop icomp = 1 v, isense = 0 v, v olp 0.77 0.82 0.86 protection (olp), vcomp = 1 v open loop protection (olp) internal vsense = 0.5 v 100 250 na pull-down current vsense threshold, output v uvd 4.63 4.75 4.87 under-voltage detection (uvd), vsense threshold, output v ovp isense = -0.2 v 5.12 5.25 5.38 over-voltage protection (ovp), v input brown-out detection (ibop) vins brownout_th 0.76 0.82 0.88 high-to-low threshold input brown-out detection (ibop) vins enable_th 1.4 1.5 1.6 low-to-high threshold i vins_0 v vins bias current vins = 0 v 0 0.1 a icomp threshold, external overload 0.6 v protection 3 submit documentation feedback www.ti.com
UCC28019 slus755 ? april 2007 electrical characteristics (continued) unless otherwise noted, vcc = 15 v dc , 0.1 m f from vcc to gnd, -40c t j = t a 125c. all voltages are with respect to gnd. currents are positive into and negative out of the specified terminal. parameter test conditions min typ max unit current loop gmi transconductance gain t a = 25c 0.75 0.95 1.15 ms output linear range 50 a icomp voltage during olp vsense = 0.5 v 3.7 4.0 4.3 v voltage loop v ref reference voltage -40c t a 125c 4.90 5.00 5.10 v gmv transconductance gain 31.5 42 52.5 s maximum sink current under normal vsense = 6 v, vcomp = 4 v 21 30 38 operation source current under soft start vsense = 4 v, vcomp = 0 v ?21 -30 -38 a vsense = 4 v, vcomp = 0 v ?100 ?170 ?250 maximum source current under edr operation vsense = 4 v, vcomp = 4 v ?60 ?100 ?140 enhanced dynamic response, v sense 4.63 4.75 4.87 v low threshold, falling v sense input bias current 1 v vsense 5 v 100 250 na v comp voltage during olp vsense = 0.5 v, i vcomp = 0.5 ma 0 0.2 0.4 v gate driver gate current, peak, sinking (1) c gate = 4.7 nf 2.0 a gate current, peak, sourcing (1) c gate = 4.7 nf ?1.5 gate rise time c gate = 4.7 nf, gate = 2 v to 8 v 40 60 ns gate fall time c gate = 4.7 nf, gate = 8 v to 2 v 25 40 gate low voltage, no load gate = 0 a 0 0.05 gate low voltage, sinking gate = 20 ma 0.3 0.8 gate low voltage, sourcing gate = -20 ma ?0.3 ?0.8 gate low voltage, sinking vcc = 5 v, gate = 5 ma 0.2 0.75 1.2 v gate low voltage, sinking vcc = 5 v, gate = 20 ma 0.2 0.9 1.5 gate high voltage vcc = 20 v, c gate = 4.7 nf 11 12.5 14 gate high voltage vcc = 11 v, c gate = 4.7 nf 9.5 10.5 11.0 vcc = vcc off + 0.2 v, gate high voltage 8.0 9.0 10.2 c gate = 4.7 nf (1) not tested. characterized by design. 4 submit documentation feedback www.ti.com
typical characteristics UCC28019 slus755 ? april 2007 unless otherwise noted, vcc = 15 v dc , 0.1 m f from vcc to gnd, t j = t a = 25 c. all voltages are with respect to gnd. currents are positive into and negative out of the specified terminal. figure 1. figure 2. figure 3. figure 4. 5 submit documentation feedback www.ti.com 0 5 15 vcc - bias supply voltage - v 0 0.5 1.5 2.5 3.0 4.0 10 20 1.0 2.0 3.5 supply current vs bias supply voltage i vcc turn on i vcc turn off vsense = vins = 3v no gate load i vcc - supply current - ma t j - temperature - c 0 2 4 6 8 10 1 3 5 7 9 i vcc - supply current - ma supply current vs temperature operating, gate load = 4.7 nf i vcc(on_load) standby i vcc(stby) -60 -35 -10 65 115 140 15 40 90 t j - temperature - c 0 0.1 0.2 0.3 0.4 0.5 i vcc(start) - supply current - ma supply current vs temperature pre-start (i vcc(start) ) vcc = vcc on - 0.1 v -60 -35 -10 65 115 140 15 40 90 -60 -35 -10 65 115 140 t j - temperature - c 8.0 9.0 11.0 12.0 15 40 90 10.0 vcc on /vcc off - uvlo threshold - v uvlo thresholds vs temperature vcc turn off (vcc off ) vcc turn on (vcc on )
UCC28019 slus755 ? april 2007 typical characteristics (continued) figure 5. figure 6. figure 7. figure 8. 6 submit documentation feedback www.ti.com t j - temperature - c 0 0.4 0.8 1.2 1.6 2.0 gmi - gain - ma/v current averaging amplifier transconductance vs temperature gain 0.2 0.6 1.0 1.4 1.8 -60 -35 -10 65 115 140 15 40 90 t j - temperature - c 30 34 38 42 46 50 gmv - gain - a/v voltage error amplifier transconductance vs temperature 32 36 40 44 48 gain -60 -35 -10 65 115 140 15 40 90 10 16 vcc - bias supply voltage - v 55 59 63 67 71 75 f sw - switching frequency - khz oscillator frequency vs bias supply voltage 57 61 65 69 73 switching frequency 20 18 14 12 t j - temperature - c 55 59 63 67 71 75 f sw - switching frequency - khz oscillator frequency vs temperature switching frequency 57 61 65 69 73 -60 -35 -10 65 115 140 15 40 90
UCC28019 slus755 ? april 2007 typical characteristics (continued) figure 9. figure 10. figure 11. figure 12. 7 submit documentation feedback www.ti.com t j - temperature - c v soc - isense threshold - v isense threshold vs temperature soft over-current protection (soc) -60 -35 -10 65 115 140 15 40 90 0 -0.2 -0.4 -0.6 -0.8 -1.0 -0.1 -0.3 -0.5 -0.7 -0.9 t j - temperature - c 0 0.4 0.8 1.2 1.6 2.0 vins enable_th / vins brouwnout_th C vins threshold - v vins threshold vs temperature 0.2 0.6 1.0 1.4 1.8 -60 -35 -10 65 115 140 15 40 90 vins enable (vins enable_th ) input brown-out protection (vins brownout_th ) t j - temperature - c 4.50 5.25 5.50 v ovp / v uvd - vsense threshold - v vsense threshold vs temperature 4.75 5.00 under-voltage protection (v uvd ) over-voltage protection (v ovp ) -60 -35 -10 65 115 140 15 40 90 t j - temperature - c 0 0.4 0.8 1.2 1.6 2.0 v olp C vsense threshold - v vsense threshold vs temperature 0.2 0.6 1.0 1.4 1.8 -60 -35 -10 65 115 140 15 40 90 open loop protection (v olp )
UCC28019 slus755 ? april 2007 typical characteristics (continued) figure 13. figure 14. figure 15. figure 16. 8 submit documentation feedback www.ti.com 10 12 16 20 vcc - bias supply voltage - v 0 10 20 30 40 50 18 t - time - ns gate drive switching vs bias supply voltage fall time c gate = 4.7 nf v gate = 2 v - 8 v rise time 5 15 25 35 45 14 t j - temperature - c 0 0.4 0.8 1.2 1.6 2.0 v gate C gate low voltage - v gate low voltage with device off vs temperature 0.2 0.6 1.0 1.4 1.8 -60 -35 -10 65 115 140 15 40 90 v gate vcc = 5 v i vcc = 20 ma t j - temperature - c 100 200 300 400 500 600 t - time - ns minimum off time vs temperature t off(min) vsense = 3 v icomp = 1 v 105 250 350 450 550 -60 -35 -10 65 115 140 15 40 90 t j - temperature - c 0 10 20 30 40 50 t - time - ns gate drive switching vs temperature fall time c gate = 4.7 nf v gate = 2 v - 8 v rise time 5 15 25 35 45 -60 -35 -10 65 115 140 15 40 90
UCC28019 slus755 ? april 2007 typical characteristics (continued) figure 17. 9 submit documentation feedback www.ti.com t j - temperature - c 4.50 4.75 5.00 5.25 5.50 v ref - reference voltage - v reference voltage vs temperature reference voltage vcc = 15v -60 -35 -10 65 115 140 15 40 90
device information connection diagram pin descriptions UCC28019 slus755 ? april 2007 UCC28019 top view (soic-8, pdip-8) terminal functions terminal i/o function name # gate drive: integrated push-pull gate driver for one or more external power mosfets. 2.0-a sink and 1.5-a gate 8 o source capability. output voltage is clamped at 12.5 v. gnd 1 ground: device ground reference. current loop compensation: transconductance current amplifier output. a capacitor connected to gnd icomp 2 o provides compensation and averaging of the current sense signal in the current control loop. the controller is disabled if the voltage on icomp is less than 0.6 v. inductor current sense: an input for the voltage across the external current sense resistor, which represents the instantaneous current through the pfc boost inductor. this voltage is averaged to eliminate isense 3 i the effects of noise and ripple. soft over current (soc) limits the average inductor current. cycle-by-cycle peak current limit (pcl) immediately shuts off the gate drive if the peak-limit voltage is exceeded. use a 220- w resistor between this pin and the current sense resistor to limit inrush-surge currents into this pin. device supply: external bias supply input. under voltage lock out (uvlo) disables the controller until vcc exceeds a turn-on threshold of 10.5 v. operation continues until vcc falls below the turn-off (uvlo) vcc 7 threshold of 9.5 v. a ceramic by-pass capacitor of 0.1 m f minimum value should be connected from vcc to gnd as close to the device as possible for high frequency filtering of the vcc voltage. voltage loop compensation: transconductance voltage error amplifier output. a resistor-capacitor network connected from this pin to gnd provides compensation. vcomp is held at gnd until vcc, vins, and vsense all exceed their threshold voltages. once these conditions are satisfied, vcomp is charged until vcomp 5 o the vsense voltage reaches 95% of its nominal regulation level. when the enhanced dynamic response (edr) is engaged, additional current is applied to vcomp to reduce the charge time. edr additional current is inhibited during soft-start. soft-start is programmed by the capacitance on this pin. input ac voltage sense: input brown out protection (ibop) detects when the system ac-input voltage is above a user-defined normal operating level, or below a user-defined ?brown-out? level. a filtered resistor-divider network connects from this pin to the rectified-mains node. at startup the controller is disabled vins 4 i until the vins voltage exceeds a threshold of 1.5 v, initiating a soft-start. the controller is also disabled if vins drops below the brown-out threshold of 0.8 v. operation will not resume until both vins and vsense voltages exceed their enable thresholds, initiating another soft-start. output voltage sense: an external resistor-divider network connected from this pin to the pfc output voltage provides feedback sensing for output voltage regulation. a small capacitor from this pin to gnd filters high-frequency noise. standby disables the controller and discharges vcomp when the voltage at vsense drops below the enable threshold of 0.8v. an internal 100na current source pulls vsense to gnd for vsense 6 i open-loop protection (olp), including pin disconnection. output over-voltage protection (ovp) disables the gate output when vsense exceeds 105% of the reference voltage. enhanced dynamic response (edr) rapidly returns the output voltage to its normal regulation level when a system line or load step causes vsense to fall below 95% of the reference voltage. 10 submit documentation feedback www.ti.com gnd icomp isense gate vcc vsense vcomp vins 1 2 3 4 8 7 6 5
UCC28019 slus755 ? april 2007 figure 18. block diagram 11 submit documentation feedback www.ti.com + olp/standby 0.82v olp/standby + overvoltage 5.25v ovp input brown-out protection (ibop) + + vin enable_th 1.5v s q q r vin brownout_th 0.82v 5v 20k ibop + v pcl 1.08v soft over current (soc) v soc 0.73v peak current limit (pcl) soc 40k 40k + pcl -1x 300ns leading edge blanking uvlo + + vcc on 10.5v s q q r vcc off 9.5v uvlo r sense c out l bst r isense + C bridge rectifier c isense line input d bst v out c vcomp-p r vcomp c vcomp + gmv voltage error amplifier + gmi c icomp s q q r pwm comparator k pc (s) soc m 2 m 1 emi filter icomp vcomp c in 5v 65khz oscillator r load fault c vcc auxilary supply current amplifier 3 isense 2 icomp vins 4 5 vcomp 6 vsense 7 1 vcc gnd 8 gate gain m 1 edr + undervoltage 4.75v edr c vins r vins1 r vins2 vcc gate driver uvlo ibop olp s q q r pcl ovp clock pre-drive and clamp circuit r fb1 r fb2 q bst 10k r gate c vsense + fault pwm ramp m 2 min off time + ss edr fault logic fault 100a
application information UCC28019 operation UCC28019 slus755 ? april 2007 the UCC28019 is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. the UCC28019 requires few external components to operate as an active pfc pre-regulator. its trimmed oscillator provides a nominal fixed switching frequency of 65 khz, ensuring that both the fundamental and second harmonic components of the conducted-emi noise spectrum are below the en55022 conducted-band 150-khz measurement limit. its tightly-trimmed internal 5-v reference voltage provides for accurate output voltage regulation over the typical world-wide 85 v ac to 265 v ac mains input range from zero to full output load. the usable system load ranges from 100 w to 2 kw and may be extended in special situations. regulation is accomplished in two loops. the inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. under extremely light load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet class-d requirements of iec 1000-3-2 despite the higher harmonics. the outer voltage loop regulates the output voltage on vcomp (dependent upon the line and load conditions) which determines the internal gain parameters for maintaining a low-distortion steady-state input current waveshape. 12 submit documentation feedback www.ti.com
power supply UCC28019 slus755 ? april 2007 application information (continued) the UCC28019 operates from an external bias supply. it is recommended that the device be powered from a regulated auxiliary supply. this device is not intended to be used from a bootstrap bias supply. a bootstrap bias supply is fed from the input high voltage through a resistor with sufficient capacitance on vcc to hold up the voltage on vcc until current can be supplied from a bias winding on the boost inductor. the minimal hysteresis on vcc would require an unreasonable value of hold-up capacitance. during normal operation, when the output is regulated, current drawn by the device includes the nominal run current plus the current supplied to the gate of the external boost switch. decoupling of the bias supply must take switching current into account in order to keep ripple voltage on vcc to a minimum. a ceramic capacitor with a minimum value of 0.1 m f is recommended from vcc to gnd with short, wide traces. figure 19. device supply states the device bias operates in several states. during startup, vcc under-voltage lockout (uvlo) sets the minimum operational dc input voltage of the pfc controller. there are two uvlo thresholds. when the uvlo turn-on threshold is exceeded, the controller turns on. if vcc falls below the uvlo lower turn-off threshold, the controller turns off. during uvlo, current drawn by the device is minimal. after the device turns on, soft start (ss) is initiated and the output is ramped up in a controlled manner to reduce the stress on the external components and prevents output voltage overshoot. during soft start and after the output is in regulation, the device draws its normal run current. if any of several fault conditions is encountered or if the device is put in standby with an external signal, the device draws a reduced standby current. 13 submit documentation feedback www.ti.com vcc vcc on 10.5v vcc off 9.5v i vcc i vcc(start) <200 a i vcc(stby) <2.9m a i vcc(on) uvlo soft-start uvlo run run fault/standby controller state pwm state off ramp regulated off regulated off soft- start ramp
soft start system protection UCC28019 slus755 ? april 2007 application information (continued) vcomp, the output of the voltage loop transconductance amplifier, is pulled low during uvlo, ibop, and olp(open-loop protection)/standby. after the fault condition is released, soft start controls the rate of rise of vcomp in order to obtain a linear control of the increasing duty cycle as a function of time. during soft start a constant 30 a of current is sourced into the compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85% of its final value. at this point, the sourcing current begins to decrease until the output voltage reaches 95% of its final rated voltage. the soft-start time is controlled by the voltage error amplifier compensation components selected, and is user-programmable based on desired loop crossover frequency. once v out exceeds 95% of rate voltage, edr is no longer inhibited. figure 20. soft start system level protection features keep the system in safe operating limits: figure 21. output protection states 14 submit documentation feedback www.ti.com 5v vcomp vcomp fault gmv i ss = -30ua for vsense < 4.75v during soft-start + vsense feedback voltage ovp 105% v ref olp soft-start (no edr) olp ovp (no gate output) run uvd (edr on) protection state 100% v ref olp/ss 16% v ref run edr 95% v ref
vcc under-voltage lockout (uvlo) input brown-out protection (ibop) UCC28019 slus755 ? april 2007 application information (continued) during startup, uvlo keeps the device in the off state until vcc rises above the 10.5-v enable threshold, vcc on . with a typical 1 v of hysteresis on uvlo to eliminate noise, the device turns off when vcc drops to the 9.5-v disable threshold, vcc off . figure 22. uvlo the vins, (sensed input line voltage), input provides a means for the designer to set the desired mains rms voltage level at which the pfc pre-regulator should start-up, v ac(turnon) , as well as the desired mains rms level at which it should shut down, v ac(turnoff) . this prevents unwanted sustained system operation at or below a ?brown-out? voltage, where excessive line current could overheat components. in addition, because vcc bias is not derived directly from the line voltage, ibop protects the circuit from low line conditions that may not trigger the vcc uvlo turn-off. figure 23. input brown-out protection (ibop) input line voltage is sensed directly from the rectified ac mains voltage through a resistor divider filter network providing a scaled and filtered value at the vins input. ibop puts the device in standby mode when vins falls (high-to-low) below 0.8 v, vins brownout_th . the device comes out of standby when vins rises (low-to-high) above 1.5 v, vins enable_th . i vins_0 v , bias current sourced from vins, is less than 0.1 a. with a bias current this low, there is little concern for any set-point error caused by this current flowing through the sensing network. the highest reasonable value resistance for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. be aware that higher resistance values are more susceptible to noise pickup, but low noise pcb layout techniques can help mitigate this. also, depending on the resistor type used and its voltage rating, r vins1 should be implemented with multiple resistors in series to reduce voltage stresses. 15 submit documentation feedback www.ti.com + + vcc on 10.5v s q q r c decouple vcc auxilary supply gnd vcc off 9.5v uvlo input brown-out protection (ibop) + + vin enable_th 1.5 v s q q r vin brownout_th 0.82 v c vins rectified ac line r vins1 r vins2 vins 5v 20k ibop c in
UCC28019 slus755 ? april 2007 application information (continued) first, select r vins1 based on the the highest reasonable resistance value available for typical applications. then select r vins2 based on this value: where v f_bridge is the forward voltage drop across the ac rectifier bridge. power dissipated in the resistor network is: the filter capacitor, c vins , has two functions. first, to attenuate the voltage ripple to levels between the enable and brown-out thresholds which will prevent the ripple on vins from falsely triggering ibop when the converter is operating at low line. second, c vins delays the brown-out protection operation for a desired number of line half-cycle periods while still having a good response to an actual brown-out event. the capacitor is chosen so that it will discharge to the vins brownout_th level after n number of half line cycles of delay to accommodate line dropouts. where: and v in_rms(min) is the lowest normal operating rms input voltage. 16 submit documentation feedback www.ti.com 2 2 1 2 0 9 cvin _ dschg vins brownout _ th(min) vins vins in _ rms (min) vins vins t c vins r n r . v ( ) r r - = + ? ? l 2 half _ cycles cvins _ dschrg line(min) n t f = 2 1 2 enable _ th(max) vins vins ac( on ) enable _ th(max) f _ bridge vins r r v vins v = - - 2 1 2 in _ rms vins vins vins v p r r = +
output over-voltage protection (ovp) open loop protection/standby (olp/standby) output under-voltage detection (uvd) / enhanced dynamic response (edr) UCC28019 slus755 ? april 2007 application information (continued) v out(ovp) is the output voltage exceeding 5% of the rated value, causing vsense to exceed a 5.25-v threshold (5-v reference voltage + 5%), v ovp . the normal voltage control loop is bypassed and the gate output is disabled until vsense falls below 5.25 v. for example, v out(ovp) is 420 v in a system with a 400-v rated output. if the output voltage feedback components were to fail and disconnect (open loop) the signal from the vsense input, then it is likely that the voltage error amp would increase the gate output to maximum duty cycle. to prevent this, an internal pull-down forces vsense low. if the output voltage falls below 16% of its rated voltage, causing vsense to fall below 0.8 v, the device is put in standby, a state where the pwm switching is halted and the device is still on but draws standby current below 3 ma. this shutdown feature also gives the designer the option of pulling vsense low with an external switch. during large changes in load, enhanced dynamic response (edr) acts to speed up the slow response of the low-bandwidth voltage loop. figure 24. over voltage protection, open loop protection/standby 17 submit documentation feedback www.ti.com + open loop protection/ standby r fb1 output voltage standby olp/standby r fb2 + overvoltage ovp vsense optional + undervoltage uvd 4.75v 5.25v 0.82v
overcurrent protection soft over-current (soc) peak current limit (pcl) UCC28019 slus755 ? april 2007 application information (continued) inductor current is sensed by r sense , a low value resistor in the return path of input rectifier. the other side of the resistor is tied to the system ground. the voltage is sensed on the rectifier side of the sense resistor and is always negative. there are two over-current protection features; peak current limit (pcl) protects against inductor saturation and soft over current (soc) protects against an overload on the output. figure 25. soft over current (soc) / peak current limit (pcl) soc limits the input current. soc is activated when the current sense voltage on isense reaches -0.73 v, affecting the internal vcomp level, and the control loop is adjusted to reduce the pwm duty cycle. peak current limit operates on a cycle-by-cycle basis. when the current sense voltage on isense reaches -1.08 v, pcl is activated terminating the active switch cycle. the voltage at isense is amplified by a fixed gain of -1.0 and then leading-edge blanked to improve noise immunity against false triggering. 18 submit documentation feedback www.ti.com pcl + v pcl 1.08v isense soft over current (soc) r sense r isense + C c isense (optional) line input v out v soc 0.73v peak current limit (pcl) soc + -1x 300ns leading edge blanking +
current sense resistor, r sense gate driver UCC28019 slus755 ? april 2007 application information (continued) the current sense resistor, r sense , is sized using the minimum threshold value of soft over current (soc), v soc(min) = 0.66 v. to avoid triggering this threshold during normal operation, taking into account the gain of the internal non-linear power limit, resulting in a decreased duty cycle, the resistor is typically sized for an overload current of 25% more than the peak inductor peak current. since r sense sees the average input current, worst-case power dissipation occurs at input low line when input line current is at its maximum. power dissipated by the sense resistor is: peak current limit (pcl) protection turns off the output driver when the voltage across the sense resistor reaches the pcl threshold, v pcl . the absolute maximum peak current, i pcl , is given as: the gate output is designed with a current-optimized structure to directly drive large values of total mosfet gate capacitance at high turn-on and turn-off speeds. an internal clamp limits voltage on the mosfet gate to 12.5 v. an external gate drive resistor, r gate , limits the rise time and dampens ringing caused by parasitic inductances and capacitances of the gate drive circuit thus reducing emi. the final value of the resistor depends upon the parasitic elements associated with the layout and other considerations. a 10-k w resistor close to the gate of the mosfet, between the gate and ground, discharges stray gate capacitance and protects against inadvertent dv/dt-triggered turn-on. figure 26. gate driver 19 submit documentation feedback www.ti.com 1 25 soc(min) sense l _ peak (max) v r . i 2 rsense in _ rms (max) sense p ( i ) r = pcl pcl sense v i r = vcc vcc gate c out l bst d bst v out rectified ac gnd r gate uvlo ibop olp from pwm latch 10k s q q r pcl ovp clock pre-drive and clamp circuit q bst fault logic
current loop isense and icomp functions pulse width modulator control logic voltage loop output sensing UCC28019 slus755 ? april 2007 application information (continued) the overall system current loop consists of the current averaging amplifier stage, the pulse width modulator (pwm) stage, the external boost inductor stage, and the external current sensing resistor. the negative polarity signal from the current sense resistor is buffered and inverted at the isense input. the internal positive signal is then averaged by the current amplifier (gmi), whose output is the icomp pin. the voltage on icomp is proportional to the average inductor current. an external capacitor to gnd is applied to the icomp pin for current loop compensation and current ripple filtering. the gain of the averaging amplifier is determined by the internal vcomp voltage. this gain is non-linear to accommodate the world-wide ac-line voltage range. icomp is connected to 4 v internally whenever the device is in a fault or standby condition. the pwm stage compares the icomp signal with a periodic ramp to generate a leading-edge-modulated output signal which is high whenever the ramp voltage exceeds the icomp voltage. the slope of the ramp is defined by a non-linear function of the internal vcomp voltage. the pwm output signal always starts low at the beginning of the cycle, triggered by the internal clock. the output stays low for a minimum off-time, t off(min) , after which the ramp rises linearly to intersect the icomp voltage. the ramp-i comp intersection determines t off , and hence d off . since d off = v in /v out by the boost-topology equation, and since v in is sinusoidal in wave-shape, and since icomp is proportional to the inductor current, it follows that the control loop forces the inductor current to follow the input voltage wave-shape to maintain boost regulation. therefore, the average input current is also sinusoidal in wave-shape. the output of the pwm comparator stage is conveyed to the gate drive stage, subject to control by various protection functions incorporated into the ic. the gate output duty-cycle may be as high as 99%, but will always have a minimum off-time t off(min) . normal duty-cycle operation can be interrupted directly by ovp and pcl on a cycle-by-cycle basis. uvlo, ibop and olp/standby also terminate the gate output pulse, and further inhibit output until the ss operation can begin. the outer control loop of the pfc controller is the voltage loop. this loop consists of the pfc output sensing stage, the voltage error amplifier stage, and the non-linear gain generation. a resistor-divider network from the pfc output voltage to gnd forms the sensing block for the voltage control loop. the resistor ratio is determined by the desired output voltage and the internal 5-v regulation reference voltage. like the vins input, the very low bias current at the vsense input allows the choice of the highest practicable resistor values for lowest power dissipation and standby current. a small capacitor from vsense to gnd serves to filter the signal in a high-noise environment. this filter time constant should generally be less than 100 m s. 20 submit documentation feedback www.ti.com
voltage error amplifier non-linear gain generation UCC28019 slus755 ? april 2007 application information (continued) the transconductance error amplifier (gmv) generates an output current proportional to the difference between the voltage feedback signal at vsense and the internal 5-v reference. this output current charges or discharges the compensation network capacitors on the vcomp pin to establish the proper vcomp voltage for the system operating conditions. proper selection of the compensation network components leads to a stable pfc pre-regulator over the entire ac-line range and 0-100% load range. the total capacitance also determines the rate-of-rise of the vcomp voltage at soft start, as discussed earlier. the amplifier output vcomp is pulled to gnd during any fault or standby condition to discharge the compensation capacitors to an initial zero state. usually, the large capacitor has a series resistor which delays complete discharge by their respective time constant (which may be several hundred milliseconds). if vcc bias voltage is quickly removed after uvlo, the normal discharge transistor on vcomp loses drive and the large capacitor could be left with substantial voltage on it, negating the benefit of a subsequent soft-start. the UCC28019 incorporates a parallel discharge path which operates without vcc bias, to further discharge the compensation network after vcc is removed. when output voltage perturbations greater than 5% appear at the vsense input, the amplifier moves out of linear operation. on an over-voltage, the ovp function acts directly to shut off the gate output until vsense returns within 5% of regulation. on an under-voltage, the uvd function invokes edr which immediately increases the internal vcomp voltage by 2 v and increases the external vcomp charging current typically to 100 m a to 170 m a. this higher current facilitates faster charging of the compensation capacitors to the new operating level, improving transient response time. the voltage at vcomp is used to set the current amplifier gain and the pwm ramp slope. this voltage is buffered internally and is then subject to modification by the edr function and the soc function, as discussed earlier. together the current gain and the pwm slope adjust to the different system operating conditions (set by the ac-line voltage and output load level) as vcomp changes, to provide a low-distortion, high-power-factor input current wave-shape following that of the input voltage. 21 submit documentation feedback www.ti.com
layout guidelines UCC28019 slus755 ? april 2007 application information (continued) as with all pwm controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. the pinout of the UCC28019 is ideally suited for separating the high di/dt induced noise on the power ground from the low current quiet signal ground required for adequate noise immunity. a star point ground connection at the gnd pin of the device can be achieved with a simple cut out in the ground plane of the printed circuit board. as shown in figure 27 , the capacitors on isense, vins, vcomp, and vsense (c11, c12, c15, c17, and c16, respectively) must all be returned directly to the quiet portion of the ground plane, indicated by signal gnd, and not the high current return path of the converter, shown as the power gnd. because the example circuit in figure 27 uses surface mount components, the icomp capacitor, c10, has its own dedicated return to the gnd pin. figure 27. recommended layout for the UCC28019 22 submit documentation feedback www.ti.com cut out in ground plane signal gnd power gnd gnd icomp isense vins vcomp vsense vcc gate
design example 350-w, universal input, 390-v dc output, pfc converter design goals UCC28019 slus755 ? april 2007 this example illustrates the design process and component selection for a continuous conduction mode power factor correction boost converter utilizing the UCC28019. the target design is a universal input, 350w pfc designed for an atx supply application. this design process is directly tied to the UCC28019 design calculator spreadsheet that can be found in the tools section of the UCC28019 product folder on the texas instruments website. table 1. design goal parameters parameter test condition min typ max unit input characteristics input voltage v in 85 115 265 vac input frequency f line 47 63 hz v ac(on) 75 i out = 0.9 a brown out voltage vac v ac(off) 65 i out = 0.9 a output characteristics v out 85 vac v in 265 vac output voltage 370 390 410 vdc 47 hz f line 63 hz 0 a i out 0.9 a 85 vac v in 65vac line regulation 5% i out = 0.440 a v in = 115 vac, f line = 60 hz 5% 0 a i out 0.9 a load regulation v in = 230 vac, f line = 50 hz 5% 0 a i out 0.9 a v ripple(sw) v in = 115 vac, f line = 60 hz 3.9 i out = 0.9 a high frequency output voltage ripple v ripple(sw) v in = 230 vac , f line = 50 hz 3.9 i out = 0.9 a vpp v ripple(f_line) v in = 115 vac, f line = 60 hz, 19.5 i out = 0.9 a line frequency output voltage ripple v ripple(f_line) v in = 230 vac, f line = 50 hz 19.5 i out = 0.9 a i out output load current 85 vac v in 265 vac 0.9 a 47 hz f line 63 hz output power p out 350 w output over voltage protection v out(ovp) 410 v output under voltage protection v out(uvp) 370 23 submit documentation feedback www.ti.com
UCC28019 slus755 ? april 2007 design example (continued) table 1. design goal parameters (continued) parameter test condition min typ max unit control loop characteristics switching frequency f sw , t j = 25 c 61.7 65 68.3 khz f (co) control loop bandwidth 10 hz v in = 162 vdc, i out = 0.45 a phase margin v in = 162 vdc, i out = 0.45 a 70 degrees pf power factor 0.99 v in = 115 vac, i out = 0.9 a thd v in = 115 vac, f line = 60 hz 4.13% 10% i out = 0.9 a total harmonic distortion thd v in = 230 vac, f line = 50 hz 6.67% 10% i out = 0.9 a h full load efficiency v in = 115 vac, f line = 60 hz, 0.92 i out = 0.9 a ambient temperature t amb 50 c 24 submit documentation feedback www.ti.com
UCC28019 slus755 ? april 2007 the following procedure refers to the schematic shown in figure 28 . figure 28. design example schematic 25 submit documentation feedback www.ti.com + +
current calculations bridge rectifier UCC28019 slus755 ? april 2007 first, determine the maximum average output current, i out(max) : the maximum input rms line current, i in_rms(max) , is calculated using the parameters from table 1 and the efficiency and power factor initial assumptions: based upon the calculated rms value, the maximum peak input current, i in_peak(max) , and the maximum average input current, i in_avg(max) , assuming the waveform is sinusoidal, can be determined. assuming a forward voltage drop, v f_bridge , of 0.95 v across the rectifier diodes, br1, the power loss in the input bridge, p bridge , can be calculated: 26 submit documentation feedback www.ti.com 2 bridge f _ bridge in _ avg(max) p v i = 2 0 95 4 07 7 73 bridge p . v . a . w = = 2 6 39 4 07 in _ avg(max) . a i . a p = = 350 4 52 0 92 85 0 99 in _ rms (max) w i . a . v . = = 2 in _ peak (max) in _ rms (max) i i = 2 4 52 6 39 in _ peak (max) i . a . a = = 2 in _ peak (max) in _ avg(max) i i p = out (max) out (max) out p i v = 350 0 9 390 out (max) w i . a v = @ out (max) in _ rms (max) in (min) p i v pf h =
input capacitor UCC28019 slus755 ? april 2007 note that the UCC28019 is a continuous conduction mode controller and as such the inductor ripple current should be sized accordingly. allowing an inductor ripple current, i ripple , of 20% and a high frequency voltage ripple factor, v ripple_in , of 6%, the maximum input capacitor value, c in , is calculated by first determining the input ripple current, i ripple , and the input voltage ripple, v in_ripple(max) : the value for the input x-capacitor can now be calculated: 27 submit documentation feedback www.ti.com 1 28 0 341 8 65 7 21 in . a c . f khz . v m = = 8 ripple in sw in _ ripple(max) i c f v = 0 06 375 7 21 in _ ripple(max) v . v . v = = 2 265 375 in _ rectified(max) v v v = = 0 06 ripple _ in v . d = 2 in _ rectified in v v = 0 2 6 39 1 28 ripple i . . a . a = = in _ ripple(max) ripple _ in in _ rectified(max) v v v = d ripple ripple in _ peak (max) i i i = d 0 2 ripple i . d =
boost inductor boost diode UCC28019 slus755 ? april 2007 the boost inductor, l bst , is selected after determining the maximum inductor peak current, i l_peak(max) : the minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5: the actual value of the boost inductor that will be used is 1.25 mh. the maximum duty cycle, duty (max) , can be calculated and will occur at the minimum input voltage: the diode losses are estimated based upon the forward voltage drop, v f , at 125 c and the reverse recovery charge, q rr , of the diode. using a silicone carbide diode, although more expensive, will essentially eliminate the reverse recovery losses: 28 submit documentation feedback www.ti.com 125 1 5 f _ c v . v = 0 rr q nc = 1 5 0 897 0 5 65 390 0 1 35 diode p . v . a . khz v nc . w = + = 2 85 120 in _ rectified(min) v v v = = 390 120 0 692 390 (max) v v duty . v - = = 125 0 5 diode f _ c out (max) sw ( typ ) out rr p v i . f v q = + out in _ rectified(min) (max) out v v duty v - = 390 0 5 1 0 5 1 17 65 1 28 bst (min) v . ( . ) l . mh khz . a - 3 3 1 28 6 39 7 03 2 l _ peak (max) . a i . a . a = + = 1 out bst (min) sw ( typ ) ripple v d( d ) l f i - 3 2 ripple l _ peak (max) in _ peak (max) i i i = +
switching element UCC28019 slus755 ? april 2007 the conduction losses of the switch are estimated using the r ds(on) of the fet at 125 c , found in the fet data sheet, and the calculated drain to source rms current, i ds_rms : the switching losses are estimated using the rise time of the gate, t r , and the output capacitance losses. for the selected device: total fet losses: 29 submit documentation feedback www.ti.com 125 0 35 dson( c ) r . = w 16 2 3 out (max) in _ rectified(min) ds _ rms in _ rectified(min) out p v i v v p = - 2 125 cond ds _ rms dson( c ) p i r = 4 5 r t . ns = 4 38 4 59 8 97 cond sw p p . w . w . w + = + = 2 65 4 5 390 6 39 0 5 780 390 4 59 sw p khz( . ns v . a . pf v ) . w = + = 2 0 5 sw sw ( typ ) r out in _ peak (max) oss out p f ( t v i . c v ) = + 780 oss c pf = 350 16 120 2 3 54 120 3 390 ds _ rms w v i . a v v p = - = 2 3 54 0 35 4 38 cond p . a . . w = w =
sense resistor UCC28019 slus755 ? april 2007 to accommodate the gain of the internal non-linear power limit, r sense , is sized such that it will trigger the soft over-current at 25% higher than the maximum peak inductor current using the minimum soc threshold, v soc , of isense. using a parallel combination of available standard value resistors, the sense resistor is chosen. the power dissipated across the sense resistor, p rsense , must be calculated: the peak current limit, pcl, protection feature will be triggered when current through the sense resistor results in the voltage across r sense to be equal to the v pcl threshold. for a worst case analysis, the maximum v pcl threshold is used: to protect the device from inrush current, a standard 220-m w resistor, r isense , is placed in series with the isense pin. a 1000-pf capacitor is placed close to the device to improve noise immunity on the isense pin. 30 submit documentation feedback www.ti.com 1 15 17 25 0 067 pcl . v i . a . = = w pcl pcl sense v i r = 2 4 52 0 067 1 36 rsense p . a . . w = w = sense rms in rsense r i p 2 (max) _ = 0 067 sense r . = w 0 66 0 075 7 03 1 25 sense . v r . . a . = = w 1 25 soc sense l _ peak (max) v r i . =
output capacitor UCC28019 slus755 ? april 2007 the output capacitor, c out , is sized to meet holdup requirements of the converter. assuming the downstream converters require the output of the pfc stage to never fall below 300 v, v out_holdup(min) , during one line cycle, t holdup = 1/f line(min) , the minimum calculated value for the capacitor is: it is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 m f. setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. the maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current of the output capacitor are calculated: the required ripple current rating at twice the line frequency is equal to: there will also be a high frequency ripple current through the output capacitor: the total ripple current in the output capacitor is the combination of both and the output capacitor must be selected accordingly: 31 submit documentation feedback www.ti.com 2 2 2 out holdup out (min) out out _ holdup(min) p t c v v 3 - 2 0 9 0 635 2 cout _ fline . a i . a = = 16 1 5 3 out cout _ hf out (max) in _ rectified(min) v i i . v p = - 0 9 11 26 2 47 270 out _ ripple( pp ) . a v . v ( hz ) f p m = = 2 2 out (max) cout _ fline i i = 2 out out _ ripple( pp ) line(min) out i v ( f )c p = 0 05 390 19 5 out _ ripple( pp ) pp v . v . v < < 0 05 out _ ripple( pp ) out v . v < 2 2 2 350 21 28 240 390 300 out (min) w . ms c f v v m 3 3 - 16 390 0 9 1 5 1 8 3 120 cout _ hf v i . a . . a v p = - = 2 2 2 cout _ rms ( total ) cout _ fline cout _ hf i i i = + 2 2 0 635 1 8 1 9 cout _ rms ( total ) i . a . a . a = + =
output voltage set point UCC28019 slus755 ? april 2007 for low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 m w for the top voltage feedback divider resistor, r fb1 . multiple resistors in series are used due to the maximum allowable voltage across each. using the internal 5-v reference, v ref , select the bottom divider resistor, r fb2 , to meet the output voltage design goals. using 13 k w for r fb2 results in a nominal output voltage set point of 391 v. the over-voltage protection, ovd, will be triggered when the output voltage exceeds 5% of its nominal set-point: the under-voltage detection, uvd, will be triggered when the output voltage falls below 5% of its nominal set-point: a small capacitor on vsense must be added to filter out noise that would trigger the enhanced dynamic response in a no-load high-line configuration. limit the value of the filter capacitor such that the rc time constant is less than 0.1ms so as not to significantly reduce the control response time to output voltage deviations. 32 submit documentation feedback www.ti.com 2 5 1 13 04 390 5 fb v m r . k v v w = = w - 1 2 2 fb fb out ( ovp ) ovp fb r r v vsense r ? ? + = ? ? 1 13 5 25 410 7 13 out ( ovp ) m k v . v . v k w + w ? ? = = ? w ? 1 2 2 fb fb out ( uvd ) uvd fb r r v vsense r ? ? + = ? ? 1 13 4 75 371 6 13 out ( uvd ) m k v . v . v k w + w ? ? = = ? w ? 1 2 ref fb fb out ref v r r v v = -
loop compensation UCC28019 slus755 ? april 2007 the selection of compensation components, for both the current loop and the voltage loop, is made easier by using the UCC28019 design calculator spreadsheet that can be found in the tools section of the UCC28019 product folder on the texas instruments website. the current loop is compensated first by determining the product of the internal loop variables, m 1 m 2 , using the internal controller constants k 1 and k fq : the vcomp operating point is found on figure 29 . the design calculator spreadsheet enables the user to iteratively select the appropriate vcomp value. figure 29. m 1 m 2 vs. vcomp for the given m 1 m 2 of 0.372 v/ m s, the vcomp, approximately equal to 4, as shown in figure 29 . 33 submit documentation feedback www.ti.com 1 15 385 65 fq k . s khz m = = 1 7 k = 1 fq sw ( typ ) k f = 2 1 1 2 2 2 out (max) out sense in _ rms fq i v r k m m v k h = 2 1 2 2 2 0 9 390 0 067 7 0 372 0 92 115 15 385 . a v . v m m . . v . s s m m w = = vcomp - v 0 0.4 0.8 1.2 1.6 2.0 m 1 m 2 m 1 m 2 vs vcomp 0.2 0.6 1.0 1.4 1.8 0 1 2 5 7 3 4 6
UCC28019 slus755 ? april 2007 the individual loop factors, m 1 which is the current loop gain factor, and m 2 which is the voltage loop pwm ramp slope, are calculated using the following conditions: the m 1 current loop gain factor: the m 2 pwm ramp slope: 34 submit documentation feedback www.ti.com 1 0 2 0 064 if : vcomp then : m . < < = 1 2 3 0 139 0 214 if : vcomp then : m . vcomp . < = - 1 3 5 5 0 279 0 632 if : vcomp . then : m . vcomp . < = - 1 5 5 7 0 903 if : . vcomp then : m . < = 1 4 0 279 4 0 632 0 484 vcomp m . . . = = - = 2 0 1 5 0 if : vcomp . v then : m s m < < = 2 2 1 5 5 6 0 1223 1 5 if : . vcomp . v then : m . (vcomp . ) s m < = - 2 5 6 7 2 056 if : . vcomp v then : m . s m < = 2 2 4 0 1223 4 1 5 0 764 vcomp v v m . ( . ) . s s m m = = - =
UCC28019 slus755 ? april 2007 verify that the product of the individual gain factors is approximately equal to the m 1 m 2 factor determined above, if not, reselect vcomp and recalculate m 1 m 2 . the non-linear gain variable, m 3 , can now be calculated: the frequency of the current averaging pole, f iavg , is chosen to be at 9.5 khz. the required capacitor on icomp, c icomp , for this is determined using the transconductance gain, gmi, of the internal current amplifier: 35 submit documentation feedback www.ti.com 1 2 0 484 0 764 0 37 v v m m . . . s s m m = = 1 2 0 37 0 372 v v . m m . s s m m @ = 2 3 0 3 0 0510 0 1543 0 1167 if : vcomp then : m . vcomp . vcomp . < < = - - 2 3 3 7 0 1026 0 3596 0 3085 if : vcomp then : m . vcomp . vcomp . < = - + 2 3 4 0 1026 4 0 3596 4 0 3085 0 512 vcomp m . . . . = = - + = 1 1 2 icomp iavg gmim c k f p = 0 95 0 484 1100 7 2 9 5 icomp . ms . c pf . khz p = =
UCC28019 slus755 ? april 2007 the transfer function of the current loop can be plotted: figure 30. bode plot of the current averaging circuit. 36 submit documentation feedback www.ti.com 1 2 1 1 2 1 1 sense out cl icomp fq bst k r v g ( f ) s( f ) k c k m m l s( f ) gmim = + ( ) 20 cldb cl g ( f ) log g ( f ) = 1*10 4 q g cl (f) f - hz -100 -60 -20 20 60 100 g cldb (f) current averaging circuit -80 -40 0 40 80 10 100 1*10 3 1*10 6 1*10 5 -180 -160 -140 -120 -100 -80 gain phase
UCC28019 slus755 ? april 2007 the open loop of the voltage transfer function, g vl (f) contains the product of the voltage feedback gain, g fb , and the gain from the pulse width modulator to the power stage, g pwm_ps , which includes the pulse width modulator to power stage pole, f pwm_ps . the plotted result is shown in figure 31 . 37 submit documentation feedback www.ti.com 2 1 2 fb fb fb fb r g r r = + 13 0 013 1 13 fb k g . m k w = = w + w 3 1 2 1 2 1 2 pwm _ ps sense out out fq in ( typ ) f k r v c k m m v p = 3 2 1 1 589 7 0 067 390 270 2 15 385 0 484 0 764 115 pwm _ ps f . hz . v f v . s . . v s m p m m = = w 3 1 2 1 1 2 out pwm _ ps pwm _ ps m v m m s g ( f ) s( f ) f m p = + vl fb pwm _ ps g ( f ) g g ( f ) = ( ) 20 vldb vl g ( f ) log g ( f ) =
UCC28019 slus755 ? april 2007 figure 31. bode plot of the open loop voltage transfer function 38 submit documentation feedback www.ti.com 1*10 4 q g vl (f) f - hz -60 20 g vldb (f) open loop voltage transfer function -40 -20 0 10 100 1*10 3 -100 -80 -60 -40 -20 0 1 0.1 0.01 gain phase
UCC28019 slus755 ? april 2007 the voltage error amplifier is compensated with a zero, f zero , at the f pwm_ps pole and a pole, f pole , placed at 20 hz to reject high frequency noise and roll off the gain amplitude. the overall voltage loop crossover, f v , is desired to be at 10 hz. the compensation components of the voltage error amplifier are selected accordingly. from figure 31 , and the design calculator spreadsheet, the open loop gain of the voltage transfer function at 10 hz is approximately 0.709 db. estimating that the parallel capacitor, c vcomp_p , is much smaller than the series capacitor, c vcomp , the unity gain will be at f v , and the zero will be at f pwm_ps , the series compensation capacitor is determined: a 3.3- m f capacitor is used for c vcomp . a 33-k w resistor is used for r vcomp . a 0.22- m f capacitor is used for c vcomp_p . 39 submit documentation feedback www.ti.com 3 3 0 258 2 20 33 3 3 1 vcomp _ p . f c . f hz k . f m m p m = = w - 1 2 zero vcomp vcomp f r c p = 1 2 pole vcomp vcomp vcomp _ p vcomp vcomp _ p f r c c c c p = + ( ) 1 1 vcomp vcomp ea vcomp vcomp vcomp _ p vcomp vcomp _ p vcomp vcomp _ p s( f )r c g ( f ) gmv r c c c c s( f ) s( f ) c c + = ? ? + + ? ? + ? ? ? ? ? 10 v f hz = 20 10 2 g ( f ) vldb v pwm _ ps vcomp v f gmv f c f p = 0 709 20 10 42 1 589 3 88 10 2 10 . db vcomp hz s . hz c . f hz m m p = = 1 2 vcomp zero vcomp r f c p = 1 30 36 2 1 589 3 3 vcomp r . k . hz . f p m = = w 2 1 vcomp vcomp _ p pole vcomp vcomp c c f r c p = -
UCC28019 slus755 ? april 2007 the total closed loop transfer function, g vl_total , contains the combined stages and is plotted in figure 32 . figure 32. closed loop voltage bode plot 40 submit documentation feedback www.ti.com vl _ total fb pwm _ ps ea g ( f ) g ( f )g ( f )g ( f ) = ( ) 20 vl _ totaldb vl _ total g ( f ) log g ( f ) = 1*10 4 f - hz -150 100 g vl_totaldb (f) closed loop voltage transfer function -50 0 50 10 100 1*10 3 0 20 40 60 80 100 1 0.1 0.01 -100 q g vl_total (f) gain phase
brown out protection UCC28019 slus755 ? april 2007 select the top divider resistor into the vins pin so as not to contribute excessive power loss. the extremely low bias current into vins means the value of r vins1 could be hundreds of megaohms. for practical purposes, a value less than 10 m w is usually chosen. assuming approximately 150 times the input bias current through the resistor dividers will result in an r vins1 that is less than 10 m w , so as to not contribute excessive noise, and still maintain minimal power loss. the brown out protection will turn off the gate drive when the input falls below the user programmable minimum voltage, v ac(off) , and turn on when the input rises above v ac(on) . a 6.5-m resistance is chosen. 41 submit documentation feedback www.ti.com 0 150 vins vins _ v i i = 150 0 1 150 vins i . a a m m = = 75 ac( on ) v v = 65 ac ( off ) v v = 1 2 ac( on ) f _ bridge enable _ th(max) vins vins v v vins r i - - = 1 2 75 0 95 1 6 6 9 150 vins v . v . v r . m a m - - = = w 1 2 2 enable _ th(max) vins vins ac( on ) enable _ th(max) f _ bridge vins r r v vins v = - - 2 1 6 6 5 100 2 75 1 6 0 95 vins . v . m r k v . v . v w = = w - -
UCC28019 slus755 ? april 2007 the capacitor on vins, c vins , is selected so that it's discharge time is greater than the output capacitor hold up time. c out was chosen to meet one-cycle hold-up time so c vins will be chosen to meet 2.5 half-line cycles. 42 submit documentation feedback www.ti.com 2 half _ cycles cvins _ dischrg line (min) n t f = 2 5 25 6 2 47 cvins _ dischrg . t . ms hz = = 2 2 1 2 0 9 cvins _ dischrg vins brownout _ th(min) vins vins in _ rms (min) vins vins t c vins r ln r . v r r - = ? ? ? + ? ? ? 25 6 0 63 0 76 100 100 0 9 85 6 5 100 vins . ms c . f . v k ln k . v . m k m - = = w w ? ? ? w + w ? ? ?
references related products UCC28019 slus755 ? april 2007 these references, additional design tools, and links to additional references, including design software and models may be found on the web at http://www.power.ti.com under technical documents. evaluation module, 350-w universal input, 390-v dc output pfc converter, texas instruments literature no. slua272 design spreadsheet, UCC28019 design calculator, texas instruments the following parts have characteristics similar to the UCC28019 and may be of interest. related products device description ucc3817/18 full-feature pfc controller uc2853a 8-pin ccm pfc controller 43 submit documentation feedback www.ti.com
tape and reel information package materials information www.ti.com 17-may-2007 pack materials-page 1
device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant UCC28019dr d 8 fmx 330 0 6.4 5.2 2.1 8 12 pkgorn t1tr-ms p tape and reel box information device package pins site length (mm) width (mm) height (mm) UCC28019dr d 8 fmx 342.9 336.6 20.6 package materials information www.ti.com 17-may-2007 pack materials-page 2
mechanical data mpdi001a january 1995 revised june 1999 post office box 655303 ? dallas, texas 75265 p (r-pdip-t8) plastic dual-in-line 8 4 0.015 (0,38) gage plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom max 0.430 (10,92) 4040082/d 05/98 0.200 (5,08) max 0.125 (3,18) min 5 0.355 (9,02) 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 for the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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